As semiconductor technology continues to inch closer to practical limitations in terms of increases in clock speed, architects are increasingly focusing on parallelism in processor architectures to obtain performance improvements. At the chip level, multiple processor cores are often disposed on the same chip, functioning in much the same manner as separate processor chips, or to some extent, as completely separate computers. In addition, even within cores, parallelism is employed through the use of multiple execution units that are specialized to handle certain types of operations. Pipelining is also employed in many instances so that certain operations that may take multiple clock cycles to perform are broken up into stages, enabling other operations to be started prior to completion of earlier operations. Multithreading is also employed to enable multiple instruction streams to be processed in parallel, enabling more overall work to performed in any given clock cycle.
One area where parallelism continues to be exploited is in the area of execution units, e.g., fixed point or floating point execution units. Many floating point execution units, for example, are deeply pipelined. However, while pipelining can improve performance, pipelining is most efficient when the instructions processed by a pipeline are not dependent on one another, e.g., where a later instruction does not use the result of an earlier instruction. Whenever an instruction operates on the result of another instruction, typically the later instruction cannot enter the pipeline until the earlier instruction has exited the pipeline and calculated its result. The later instruction is said to be dependent on the earlier instruction, and phenomenon of stalling the later instruction waiting for the result of an earlier instruction is said to introduce “bubbles,” or cycles where no productive operations are being performed, into the pipeline.
One technique that may be used to extract higher utilization from a pipelined execution unit and remove unused bubbles is to introduce multithreading. In this way, other threads are able to issue instructions into the unused slots in the pipeline, which drives the utilization and hence the aggregate throughput up. Another popular technique for increasing performance is to use a single instruction multiple data (SIMD) architecture, which is also referred to as ‘vectorizing’ the data. In this manner, operations are performed on multiple data elements at the same time, and in response to the same SIMD instruction. A vector execution unit typically includes multiple processing lanes that handle different datapoints in a vector and perform similar operations on all of the datapoints at the same time. For example, for an architecture that relies on quad(4)word vectors, a vector execution unit may include four processing lanes that perform the identical operations on the four words in each vector.
The aforementioned techniques may also be combined, resulting in a multithreaded vector execution unit architecture that enables multiple threads to issue SIMD instructions to a vector execution unit to process “vectors” of data points at the same time. Typically, a scheduling algorithm is utilized in connection with issue logic to ensure that each thread is able to proceed at a reasonable rate, with the number of bubbles in the execution unit pipeline kept at a minimum.
While conventional scheduling algorithms are typically capable of minimizing bubbles and thus maximizing the utilization of an execution unit, instructions are still issued from threads at a fraction of the rate that could otherwise be issued were greater execution bandwidth available. With N threads available from an N-way multithreaded instruction unit, an issue unit could be designed to issue up to N instructions per cycle. With a conventional single pipelined execution unit, however, only one instruction can enter the pipeline and begin execution each cycle.
Addressing the disparity between instruction issue and instruction execution bandwidth could theoretically be addressed in several manners. For example, multiple execution units could be serviced by the same issue unit. In the alternative, an execution unit could be overclocked to operate at a faster rate than the multithreaded issue unit. Neither potential solution, however, is practical for some applications. The former solution would occupy substantially greater area on a chip and would consume significantly more power. The latter solution, while not presenting many of the same concerns with respect to chip area, would still increase power consumption due to the faster operating rate. In many applications, particularly low power and portable applications, however, the additional power consumption would be highly undesirable. It would be beneficial to be able to utilize a design for an execution unit that is capable of addressing both instruction execution bandwidth and power consumption concerns.